Numerous charge sharing and charge recycling techniques are known including precharging and sharing charge between bit lines, charge recycling by switching between various power supply levels in charge pumped circuits, and various bus and circuit stacking techniques, as well as combinations of all of these techniques.
Charge sharing techniques have previously been employed in integrated circuit designs in order to save operating power. A typical circuit example is one utilized in conjunction with dynamic random access memory (DRAM) array bitlines which are precharged to a level of VCC/2 then driven to VCC (supply voltage level) or VSS (circuit ground) for the bit line (BL) and complementary bit line bar (/BL or BLB) depending on the state of the previously stored data.
Other contemporary circuit examples include the use of three groups of logic gates operating at three different voltage ranges. In operation, one group will transition from VCC/3 to VSS, the second group from 2VCC/3 to VCC/3 and the third group from VCC to 2VCC/3. In this manner, these three groups of logic gates can charge share with their adjacent voltage range group., but conventional designs are constrained to operate in this manner. Stated another way, with current circuit techniques the low level of signal or circuit block A is set equal to the high level of the adjacent signal or circuit block B.
A typical prior art charge sharing circuit is shown in FIG. 1, which is a specific implementation for a DRAM circuit. At the left and right of the circuit are the local data read lines (DRL/DRBL, DRR/DRBR) and at the center of the circuit are the global data read lines (GDR/GDRB). Thus, the function of the circuit shown in FIG. 1 is to charge share between the local data read lines, and to provide a signal on the global data read lines for the purpose of reducing current consumption and power dissipation.
Charge sharing circuit 100 includes a CDAMP amplifier circuit 102 having an input coupled to a first bus pair DRL/DRBL. The output of CDAMP amplifier circuit 102 is coupled to a first driven bus pair DAL/DABL. Amplifier circuit 102 receives the VEQ1 and VEQ2 equalization voltages, and the PRE22L, PRE11L, PREBL, and DRLATBL control signals. Amplifier circuit 102 drives the DRL and DRBL signals onto the DAL and DABL lines under control of the various control signals. Similarly, charge-sharing circuit 100 includes a CDAMP amplifier circuit 106 having an input coupled to a second bus pair DRR/DRBR. The output of CDAMP amplifier circuit 106 is coupled to a second driven bus pair DAR/DABR. Amplifier circuit 106 receives the VEQ1 and VEQ2 equalization voltages, and the PRE22R, PRE11R, PREBR, and DRLATBR control signals. Amplifier circuit 106 drives the DRR and DRBR signals onto the DAR and DABR lines under control of the various control signals. The GDRV driver circuit 104 is coupled to the DAL/DABL and DAR/DABR bus pairs, and outputs the charge-shared signal on the GDR/GDRB bus pair. The VEQ1 and VEQ2 equalization voltages are provided by EQCAP circuit 108.
Prior art charge sharing circuits such as those shown in FIG. 1 do not have a means for holding input bus voltage levels during long standby or inactive periods. Holding the voltage levels constant during inactive times is important because of the increase in transistor leakage currents with today's advanced IC technologies. Prior art charge sharing circuits also do not have any means for multiplexing or selecting which electrical signals that will have their charge shared.
What is desired, therefore, is a charge sharing circuit that has the ability to hold the voltage level constant on input data busses during long inactive times and also has more flexible multiplexing and selecting charge sharing functions unavailable in the prior art.